1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device capable of electrically programming or erasing data and, more particularly, it relates to a memory device to be used for a stacked gate type flash EEPROM in which a negative potential is applied to the control gate for erasing data.
2. Description of the Related Art
Conventionally, hot electrons are injected from the drain into the floating gate of a flash EEPROM with a stacked gate structure for writing or storing data therein. On the other hand, negative and positive electric voltages are respectively applied to the gate and the source of the device to cause a so-called Fowler-Nordheim (F-N) tunneling current to flow from the source for erasing the stored-data.
Methods of manufacturing a flash EEPROM of the above described type have already been disclosed by the inventor of the present invention (Japanese Patent Applications KOKAI Application Nos. 3-186439 and 5-4305).
According to any of these known methods, bias voltages as typically shown in the chart of FIG. 2 are applied to the transistor (FIG. 1) of a memory cell for data storage, read or erasure. Referring to FIG. 2, Vsub denotes the electric potential of the substrate which is constantly held to 0V (ground potential), whereas Vg denotes the electric potential of the control gate that varies between -10V (for data erasure) and 12V (for date storage).
However, there is a problem concerning stress voltage as discussed below that needs to be solved for a memory device of the category under consideration before it can meet the demand for extreme down-sizing and high performance that has become so strong in recent years.
a) Voltage Vg (=-10V) to be applied to the gate for erasing data is generated by a negative voltage generating circuit as typically illustrated in FIG. 3 that is arranged in the substrate of the device. While voltage Vg is available from terminal 0 of the circuit of FIG. 3, then potential vn of node N will be reduced to -10-vth (Vn=-10-vth, where Vth is a threshold voltage (approximately 3v) of P-channel type MOS transistor 101 with the gate and the drain connected). PA1 b) If a decoding function is assigned to gate voltage Vg as disclosed in Japanese Patent Application KOKAI Publication No. 5-4305, a stress voltage equal to VSW-VBB (where VSW is the voltage of the power source of the row decoder which is approximately 5V for data erasure and VBB is a negative voltage (e.g. -10V)) is generated in the row decoder. PA1 a) either applies a first power supply voltage vcc (positive voltage) to the semiconductor substrate, a predetermined positive voltage obtained by reducing a second power supply voltage vpp (positive voltage) to the source of the transistor of the memory cell and a predetermined negative voltage to the control gate of the memory cell PA1 b) or applies a power supply voltage Vpp (positive voltage) to the semiconductor substrate and a predetermined negative voltage to the control gate of the memory device.
The stress voltage generated in a substrate makes a serious problem as devices are down-sized, because it is difficult to reduce the electric field required for the flow of an F-N tunneling current in response to the reduced size of the device.
Thus, the problem of a stress voltage generated in the substrate of a memory device of the type under consideration has provided a barrier to be overcome for realizing a small high quality memory device.